Cycle-level Simulators

Cycle-level simulators presented below are user-level simulators. System calls are translated to be run on the host machine.

All the modules composing Cycle-Level Simulators are described in the Cycle-Level Modules section. The Services used by Cycle-Level modules are defined in the Capabilities section.

Single-core PowerPC405 simulator

A simulator including a PowerPC 405 32-bit RISC CPU with a scalar 5-stage pipeline, and separated instruction and data caches.

Single-core Arm v5te simulator

A simulator including an Arm v5te 32-bit RISC CPU with a scalar 5-stage pipeline, and separated instruction and data caches.

Multi Independant Core PowerPC

A simulator including several PowerPC 405 32-bit RISC CPUs with a scalar 5-stage pipeline, and separated instruction and data caches. Each processor is connected to its own independant instruction memory.

Shared Memory PowerPC405 CMP supporting pthreads

A simulator including several PowerPC 405 32-bit RISC CPUs with a scalar 5-stage pipeline, and separated instruction and data caches. All the data and instruction caches are connected to a system bus connected to the main memory.

This simulator is able to run benchmarks using pthreads, up to a number of running threads equal to the number of CPU in the simulator.

 
simulators/cycle/start.txt · Last modified: 2008/06/24 14:33 by girbal     Back to top
Recent changes RSS feed Creative Commons License Donate Powered by PHP Valid XHTML 1.0 Valid CSS Driven by DokuWiki