This Single-core Arm v5te simulator simulator includes an Arm v5te 32-bit RISC CPU with a scalar 5-stage pipeline, and separated instruction and data caches. Both caches are connected to a main dram memory through a system bus, as shown on the figure below.

The instruction cache which does not appear on the figure is embbeded within the Arm v5te CPU module.

This simulator is available at https://unisim.org/svn/public/components/CycleLevel/simulators/arm-score.

To compile, it requires to download the whole public branch of the repository which contains all the components composing the simulator. More information can be found on the Public Branch page.

missing paragraph

• Atm v5te
• Write-back Cache
• DRAM Memory
• System BUS

• elf32-loader
• linuxos
• gdb-server debugger
• inline debugger