The PowerPC 405 module implements a PowerPC 405 five stage pipeline consisting of a fetch, decode, execute, write-back, and load write-back stage. The figure below illustrates how the different types of instruction are using each pipeline stage. For instance for load and store instructions, the execute stage is used to compute the memory address. The lifetime of each 32-bits instructions in the pipeline mainly depend on the instruction type.

This module also implements the classical PowerPC 405 static branch predictor with negative address displacement branches and unconditional branches predicted as taken. The module continue to speculatively fetch along the predicted path, and can handle simultaneously two speculative branch instructions.