Like the regular System Bus module, this module allow to route memory requests in a CMP environment based on a bus architecture. However this bus implements two different queues: One for requeust / answers coming from the CPU side, and one for the answers coming from memory side.

This bus can therefor be used in out-of-order environment without risking starvation due to high number of CPU requests.

This bus module is also compatible with bus snooping.

This bus module has a dedicated pair of ports to connect from/to the memory: inMEM and outMEM, and some pair of ports to connect from/to some cpus: inCPU[i] and outCPU[i] as shown in Figure below.

The purpose of this bus module is to forward every message received on one of its input port to every output port but the one corresponding to the incoming input port. If several messages are received in the same cycle from the CPU side, a round robin algorithm select which incoming request will be enqueued. As stated earlier memory answers have their own queue, and this queue has a higher priority thant the cpu queue.

• Parameters of the module: Details on the module template parameters.
• Interface of the module: Defines the module communication ports.
• Internals of the module: Some details about the main internal data structures and algorithms.
• Statistics of the module: List of the statistics gathered by the module.

• Source file in the repository: bus_multiqueue.sim

• Multi Queue Bus module reference manual

• Single-core PowerPC405 simulator
• Single-core Arm v5 te simulator
• Shared Memory PowerPC405 CMP