This module correspond to a dram memory and includes a dram memory controler. It receives memory requests and sends back answer for those requests once they are resolved. The dram module is compatible with bus snooping.

The dram module has a dedicated pair of port to connect from/to the memory hierarchy as shown in Figure below. The input receives the memory requests and the output port is used to send back answers to those requests.

The dram memory module has a full set of latencies that are customizable to fit a particular dram configuration. The latency of each memory request is computed out of those latencies depending on the request history: Do we have to pay the latency because we are hitting a new bank, or is it the current bank, and so on...

• Parameters of the module: Details on the module template parameters.
• Interface of the module: Defines the module communication ports.
• Internals of the module: Some details about the main internal data structures and algorithms.
• Statistics of the module: List of the statistics gathered by the module.

• Source file in the repository: dram.sim

• dram module reference manual

• Single-core PowerPC405 simulator
• Single-core Arm v5 te simulator
• Shared Memory PowerPC405 CMP