typename INSTRUCTION
The type used to store the instruction corresponding to a memory request.

int nBanks
The number of memory banks. Typically 2 or 4.

int nRows
The number of rows. Typically 2048, 4096, or 8192.

int nCols
The number of columns. Typically 256, 512 or 1024.

int TRRD
One of the memory delay latency: ACTV command in one bank to ACTV command in another bank.

int TRAS
One of the memory delay latency: ACTV command to PRE or PREALL.

int TRCD
One of the memory delay latency: ACTV command to READ, READP, WRT or WRTP command (for READP and WRTP mTRCD ¡= mTRAS).

int CL
One of the memory delay latency: CAS Latency, the time to wait before Data Out.

int TRP
One of the memory delay latency: PRE or PREALL command to ACTV, MRS, REFR, or SLFR command.

int TRC
One of the memory delay latency: ACTV, REFR or SLFR command to ACTV, MRS, REFR, or LSFR command.

uint64t TREF
One of the memory delay latency: The refresh interval.

int nCtrlQueueSize
The size of the control queue associated with the memory.

int nDataPathSize
Data Bus width in Bytes. Typically 8 bytes.

int nCacheLineSize
Line size of the connected cache. This value defines the burst size. The value is provided in bytes.

bool Snooping
Boolean value setting whether or not this module is used in a bus snooping context. The dram module an additional port to receive the shared bit information from the bus. The dram should ignore requests when when this bit is set. This parameter defaults to false (bus snooping desactivated).

bool VERBOSE = false
When this boolean parameter is set to true, some additional debugging information is printed into a log file when the memory content is changed. This parameter defaults to false (no debug information).