DRAM module interface
Clocks
inclock clock
Input clock port to receive the memory clock.
Module ports
inport < memreq < INSTRUCTION, nDataPathSize > > in
Input port receiving the requests from the memory hierarchy. Those requests are stored in the dram request queue.outport < memreq < INSTRUCTION, nDataPathSize > > out
Output port used to send request answers to the memory hierarchy.
Optional module ports
The optional ports defined below are only available if bus snooping is activated with the Snooping parameter. When bus snooping is activated, a new ports are available to receive the shared bit information. Each time a request is sent on the bus, all the connected caches combinationaly set the shared bit if they own the requested data to prevent the memory from answering. The memory should therefore ignore incoming requests when this bit is set.
inport < bool > inShared
Input port receiving the shared bit information of each CPU connected to the bus when bus snooping is activated.
