This module implements a write-back blocking cache that you can instantiate several times with different parameters to build up a full memory hierarchy. This cache module is compatible with bus snooping.

The cache module has two different sides. The side connected to the CPU (or to a lower level cache) and the side connected to the memory (or to a higher level cache). For the purpose of this documentation we’ll consider the port on the cpu side inCPU and outCPU as port connected to a cpu, and the port on the memory side inMEM and outMEM as memory ports as shown on the figure below.

The cache module has a dedicated pair of port on each side, to receive requests and send answers on the cpu side, and to send request and receive answers on the memory side.

• Parameters of the module: Details on the module template parameters.
• Interface of the module: Defines the module communication ports.
• Internals of the module: Some details about the main internal data structures and algorithms.
• Statistics of the module: List of the statistics gathered by the module.

• Source file in the repository: CacheWB.sim

• Write-back module reference manual

• Single-core PowerPC405 simulator
• Single-core Arm v5 te simulator
• Shared Memory PowerPC405 CMP