typename INSTRUCTION
The type used to store the instruction corresponding to a memory request.

int LineSize
The size of a cache line in bytes.

int nCacheLines
The number of cache lines in the cache.

int nAssociativity
The associativity level of the cache. If the value is set to nCacheLines the cache is fully associative. If the value is set to 1, the cache is direct map.

int nStages
The number of stages in the cache pipeline. If set to 1, the cache is not pipelined.

int nDelay
The delay cycles of each pipeline stage.

int nProg
The CPUID of the connected processor. Mostly used for debugging purpose.

int nCPUtoCacheDataPathSize
The maximum data size in bytes that can be received from the CPU.

int nCachetoCPUDataPathSize
The maximum data size in bytes that can be sent to the CPU.

int nCPULineSize
The minimum data size that has to be sent to the CPU side. If the cache is directly connected to the cpu, this value should be set to 0, else it should correspond to the size of the cache line in level -1. This value is used to set the base address of the requested data.

int nMemtoCacheDataPathSize
The maximum data size in bytes that can be received from the memory system.

int nCachetoMemDataPathSize
The maximum data size in bytes that can send towards the memory system.

bool Snooping
Boolean value setting whether or not this module is used in a bus snooping context. The cache module has some additional ports and processes to deal with the shared bit information when bus snooping is activated. This parameter defaults to false (bus snooping desactivated).

bool VERBOSE
When this boolean parameter is set to true, some additional debugging information is printed into a log file when the cache content is changed, may it be stored data or cache line states. This parameter defaults to false (no debug information).