• inclock clock
  Input clock port to receive the cache clock.

• inport < memreq < INSTRUCTION, nCPUtoCacheDataPathSize > > inCPU
  Input port receiving the requests from the cpu. Those requests are stored in the cache queue.
• outport < memreq < INSTRUCTION, nCachetoCPUDataPathSize > > outCPU
  Output port used to send answers from previously received requests back to the cpu.
• inport < memreq < INSTRUCTION, nMemtoCacheDataPathSize > > inMEM
  Input port receiving the answers from the memory. Those answers are updating the cache queue. In a bus snooping configuration requests from other cpus can also begin received through this port.
• outport < memreq < INSTRUCTION, nCachetoMemDataPathSize > > outMEM
  Output port used to send requests to the memory. In a bus snooping configuration this port is also used to send answers to other cache when this cache has a hit on the request address.

The optional ports defined below are only available if bus snooping is activated with the Snooping parameter. When bus snooping is activated, a new ports are available to send the shared bit information. Each time a request is sent on the bus, all the connected caches combinationaly set the shared bit if they own the requested data to prevent the memory from answering. The memory should therefore ignore incoming requests when this bit is set.

• outport <bool> outSharedMEM
  Output port used to send the shared bit information to the bus. The bus will then perform an “or” on every received bit.