Cache Coherency Protocols

MESI

Read miss
I	–StlL→	S
I	–StlH→	St	when req goes to L2 and some speculative threads have new specultive data.
S
St
M
MC

BusR
I			no invalid on bus (if answer), I→I if req
S	→	S
St			not possible for speculative threads
MC	→	S
M			not possible for speculative threads

Bus on Write hit
I
S	→	INV	ok. ditant goes to modified ⇒ invalidate, Regular MSI
St	→	INV	ok. ditant goes to modified ⇒ invalidate
M			. Distant write hit impossible on local modified
MC			impossible on write hit, only on miss

Bus on Write miss
MC	→	INV	Is there a writeback ?
S	→	INV

Word-based cache coherency:
- Let’s configure the cache to have a cache line containing only a word.
States
- which states imply you have an exclusive copy ? M MC
Read / Write Miss
- INV → S/St : It s a matter of checking an extra signal.
- Then, the mechanism of distributed arbitration chooses the supplier thread and allows it to put the requested cache word on the shared bus.
  - controller on speculation support at the bus level.

Build the FSA to be translated into source code
- Matching transitions with existing ones if possible.