System BUS interface
Clocks
inclock clock
Input clock port to receive the bus clock.
Module ports
inport < memreq < INSTRUCTION, RequestWidth > > inCPU[nCPU]
Input port receiving the messages from CPU number i. Those Messages are stored in the queue to
be broadcasted to every module connected to the bus.
outport < memreq < INSTRUCTION, RequestWidth > > outCPU[nCPU]
Output port to send messages to the CPU number i. This port is used to broadcast messages.inport < memreq < INSTRUCTION, RequestWidth > > inMEM
Input port receiving the messages from the memory. Those Messages are stored in the queue to be
broadcasted to every module connected to the bus.
outport < memreq < INSTRUCTION, RequestWidth > > outMEM
Output port to send messages to the memory. This port is used to broadcast messages.
Optional module ports
The optional ports defined below are only available if bus snooping is activated with the Snooping parameter. When bus snooping is activated, some new ports are available to send the shared bit information. Each time a request is sent on the bus, all the connected caches combinationaly set the shared bit if they own the requested data to prevent the memory from answering.
inport <bool> inSharedCPU[nCPU]
Input port receiving the shared bit information of each CPU connected to the bus when bus snooping is activated.outport <bool> outSharedMEM
Output port to send the shared bit to the memory. The memory should ignore incoming requests when this bit is set to true.
