The interface is exactly the same for all the wrapped cache modules.

• inport < memreq < INSTRUCTION, nCPUtoCacheDataPathSize > > inCPU
  Input port receiving the requests from the cpu. Those requests are stored in the cache queue.
• outport < memreq < INSTRUCTION, nCachetoCPUDataPathSize > > outCPU
  Output port used to send answers from previously received requests back to the cpu.
• inport < memreq < INSTRUCTION, nMemtoCacheDataPathSize > > inMEM
  Input port receiving the answers from the memory. Those answers are updating the cache queue. In a bus snooping configuration requests from other cpus can also begin received through this port.
• outport < memreq < INSTRUCTION, nCachetoMemDataPathSize > > outMEM
  Output port used to send requests to the memory. In a bus snooping configuration this port is also used to send answers to other cache when this cache has a hit on the request address.