http://unisim.org/site/ 2010-09-07T04:06:27+02:00 http://unisim.org/site/ http://unisim.org/site/lib/images/favicon.ico text/html 2007-08-07T13:35:37+02:00 http://unisim.org/site/modules/cycle/network/dram/interface?rev=1186486537 Clocks * inclock clock Input clock port to receive the memory clock. Module ports * inport < memreq < INSTRUCTION, nDataPathSize > > in Input port receiving the requests from the memory hierarchy. Those requests are stored in the dram request queue. * outport < memreq < INSTRUCTION, nDataPathSize > > out Output port used to send request answers to the memory hierarchy. text/html 2007-08-07T13:39:16+02:00 http://unisim.org/site/modules/cycle/network/dram/parameters?rev=1186486756 Core parameters * typename INSTRUCTION The type used to store the instruction corresponding to a memory request. * int nBanks The number of memory banks. Typically 2 or 4. * int nRows The number of rows. Typically 2048, 4096, or 8192. * int nCols The number of columns. Typically 256, 512 or 1024. * int TRRD One of the memory delay latency: ACTV command in one bank to ACTV command in another bank. * int TRAS One of the memory delay latency: ACTV command to PRE or PREALL. … text/html 2008-02-29T16:26:28+02:00 http://unisim.org/site/modules/cycle/network/dram/start?rev=1204298788 Description This module correspond to a dram memory and includes a dram memory controler. It receives memory requests and sends back answer for those requests once they are resolved. The dram module is compatible with bus snooping. The dram module has a dedicated pair of port to connect from/to the memory hierarchy as shown in Figure below. The input receives the memory requests and the output port is used to send back answers to those requests.