http://unisim.org/site/ 2010-09-11T05:02:52+02:00 http://unisim.org/site/ http://unisim.org/site/lib/images/favicon.ico text/html 2008-02-07T11:57:14+02:00 http://unisim.org/site/modules/cycle/network/cachewb/coherency_protocols?rev=1202381834 MESI MSI SISC - Non Speculative Local read Read hit I :!: DONE S -> S DONE PrRd/-- St -> St DONE PrRd/-- M -> M DONE PrRd/-- MC -> MC DONE PrRd/-- Read miss I --StlL-> S I --StlH-> St when req goes to L2 and some speculative threads have new specultive data. S :!: DONE St :!: DONE M :!: DONE MC :!: DONE Distant read BusR I :!… text/html 2007-08-07T13:31:59+02:00 http://unisim.org/site/modules/cycle/network/cachewb/interface?rev=1186486319 Clocks * inclock clock Input clock port to receive the cache clock. Module ports * inport < memreq < INSTRUCTION, nCPUtoCacheDataPathSize > > inCPU Input port receiving the requests from the cpu. Those requests are stored in the cache queue. * outport < memreq < INSTRUCTION, nCachetoCPUDataPathSize > > outCPU Output port used to send answers from previously received requests back to the cpu. * inport < memreq < INSTRUCTION, nMemtoCacheDataPathSize > > inMEM Input port receivin… text/html 2008-02-06T08:01:30+02:00 http://unisim.org/site/modules/cycle/network/cachewb/internals?rev=1202281290 Cache line state The finite state automaton below represent the possible states associated with the MESI protocol dealing with cache coherency in CMP environment based on a snooping bus. * Coherency Protocols Cache request state Read and Write requests are put in the cache queue. Those cache queue entry have a large amount of different states: For instance a read request will become a read miss, then a read miss that has been requested to the memory, then a read miss that has been ans… text/html 2007-08-07T13:31:33+02:00 http://unisim.org/site/modules/cycle/network/cachewb/parameters?rev=1186486293 Core parameters * typename INSTRUCTION The type used to store the instruction corresponding to a memory request. * int LineSize The size of a cache line in bytes. * int nCacheLines The number of cache lines in the cache. * int nAssociativity The associativity level of the cache. If the value is set to nCacheLines the cache is fully associative. If the value is set to 1, the cache is direct map. * int nStages The number of stages in the cache pipeline. If set to 1, the cache … text/html 2008-02-29T12:24:51+02:00 http://unisim.org/site/modules/cycle/network/cachewb/start?rev=1204284291 Description This module implements a write-back blocking cache that you can instantiate several times with different parameters to build up a full memory hierarchy. This cache module is compatible with bus snooping. The cache module has two different sides. The side connected to the CPU (or to a lower level cache) and the side connected to the memory (or to a higher level cache). For the purpose of this documentation we’ll consider the port on the cpu side inCPU and outCPU as port connecte… text/html 2007-09-10T18:01:57+02:00 http://unisim.org/site/modules/cycle/network/cachewb/statistics?rev=1189440117 This page describes the statistic collected by the module as defined in the Statistic Capability. As defined in the capability, statistics are 64bit unsigned interger counters. Below is a short description of each counter: * accesses Total number of accesses * accesses_read Total number of read accesses * accesses_write Total number of write accesses * accesses_prefetch Total number of prefetch accesses * accesses_evict Total number of evi…