typedef struct {
int cache_size; // cache size in bytes
int line_size; // size of one cache line in bytes
int associativity; // cache associativity ( 1 = direct mapped, 0 = fully associated )
int rw_ports; // number of read/write ports
int excl_read_ports; // number of exclusive read ports
int excl_write_ports; // number of exclusive write ports
int single_ended_read_ports; // number of single ended read ports
int banks; // number of sub-banks in cache
double tech_node; // size of tech node in micro-meters
int output_width; // number of output bits for cache
int specific_tag; // 1 if custom tag width
int tag_width; // custom tag width
int access_mode; // access mode 0 = normal, 1 = sequential access, 2 = fast access
int pure_sram; // flag, equals 1 if it's a scratch-pad memory
double freq ; // cache operating frequency, by default maximum possible based on
// calculated cycle time
} cache_input_parameter_type
int cache_size
An integer containing the total size of the cache in bytes.
int line_size
This is the size of one line of cache in bytes.
int associativity
This is the associativity for a set associative Cache. A value of 0 would mean a fully associated Cache and a value of 1 denotes a directly-mapped Cache.
int rw_ports
This is the number of read/write ports for the Cache.
int excl_read_ports
The number of exclusive read ports.
int excl_write_ports
The number of exclusive write ports.
int single_ended_read_ports
This is the number of single ended read ports.
int banks
This is the number of sub-banks in the Cache.
float tech_node
This denotes the the size of technology used for fabrication. The value is expressed in micro-meters.
int output_width
This is the number of bits used to output the data from the Cache to put on the Bus.
int specific_tag
If you want to define your own specific custom tag size, make this value 1.
int tag_width
Size of the custom tag if the preceding variable (specific_tag) is 1.
int access_mode
The mode of access to data. A value of 0 denotes normal mode, a value of 1 means the access is sequential ( data is selected after the selection of tag ) and a value of 2 would indicate fast access ( all data paths are routed towards the bus before the tag selection and the correct one is selected at the last stage ).
