Single-core PowerPC405 simulator

This Single-core PowerPC405 simulator simulator includes a PowerPC 405 32-bit RISC CPU with a scalar 5-stage pipeline, and separated instruction and data caches. Both caches are connected to a main dram memory through a system bus, as shown on the figure below.

The instruction cache which does not appear on the figure is embbeded within the PowerPC 405 CPU module.

This simulator is available at https://unisim.org/svn/public/components/CycleLevel/simulators/ppc-score.

To compile, it requires to download the whole public branch of the repository which contains all the components composing the simulator. More information can be found on the Public Branch page.

• MiBench Results

The figure below ...

More details are available for each module composing the simulator:

• PowerPC 405: The CPU embedding the 5-stage pipeline, and an instruction cache.
• Write-back Cache: A Write back data cache.
• DRAM Memory: The main memory of the simulator.
• System BUS: The system bus connecting the caches to the main memory.

• elf32-loader
• linuxos
• gdb-server debugger
• inline debugger