inclock clock outport < memreq < Instruction, nIL1CachetoMemDataPathSize > > outIL1Data inport < memreq < Instruction, nIL1MemtoCacheDataPathSize > > inIL1Data outport < memreq < Instruction, nDL1CPUtoCacheDataPathSize > > outDMEM inport < memreq < Instruction, nDL1CachetoCPUDataPathSize > > inDMEM The CPU does not have any optional port.