Cycle-level Interfaces : Signal data-types

As a structural framework, UNISIM propose to split the simulator into module components, and to promote the reuse of such components across different simulators. Modules can communicate together through ports, especially by connecting some output ports to some input ports, as shown on figure below. In such a configuration Module A can communicate with Module B by sending some data signal between the connected ports.

This part of the document will describe data types used as data signal available in the module repository. In this introduction chapter, we’ll first explain the granularity of chosen data types, and next we will present each data signal type in its own page.

• Introducing signal granularity within UNISIM

• The pipeline interface defines how to send instructions across the modules composing the pipeline stages.
  This interface is composed of the Generic Instruction signal, a generic simulator instruction type embedding the functional simulator instruction, and providing additionnal information relative to the simulator’s pipeline.

• The cpu-to-memory interface defines how to send instructions across modules composing the memory hierarchy.
  This interface is composed of the Memory Request signal, a generic type used for memory requests sent toward the memory hierarchy. This type is used both for memory request and for answers from the memory.