====== Cycle-level Simulators ======

Cycle-level simulators presented below are user-level simulators. System calls are translated to be run on the host machine.

All the modules composing Cycle-Level Simulators are described in the [[modules:cycle:intro|Cycle-Level Modules]] section. The Services used by Cycle-Level modules are defined in the [[services:start|Capabilities]] section.







===== Single-core PowerPC405 simulator =====

[[simulators:cycle:ppc-score|{{ simulators:cycle:ppc-score.png?415}}]]
A simulator including a PowerPC 405 32-bit RISC CPU with a scalar 5-stage pipeline, and separated instruction and data caches.
  * [[simulators:cycle:ppc-score|details]]
~~CL~~






===== Single-core Arm v5te simulator =====

[[simulators:cycle:arm-score|{{ simulators:cycle:arm-score.png?415}}]]
A simulator including an Arm v5te 32-bit RISC CPU with a scalar 5-stage pipeline, and separated instruction and data caches.
  * [[simulators:cycle:arm-score|details]]
~~CL~~



===== Multi Independant Core PowerPC =====

[[simulators:cycle:ppc-mcore|{{ simulators:cycle:ppc-mcore.png?415}}]]
A simulator including several PowerPC 405 32-bit RISC CPUs with a scalar 5-stage pipeline, and separated instruction and data caches. Each processor is connected to its own independant instruction memory.
  * [[simulators:cycle:ppc-mcore|details]]
~~CL~~







===== Shared Memory PowerPC405 CMP supporting pthreads =====

[[simulators:cycle:ppc-pthread|{{ simulators:cycle:ppc-pth.png?415}}]]
A simulator including several PowerPC 405 32-bit RISC CPUs with a scalar 5-stage pipeline, and separated instruction and data caches. All the data and instruction caches are connected to a system bus connected to the main memory.

This simulator is able to run benchmarks using pthreads, up to a number of running threads equal to the number of CPU in the simulator.
  * [[simulators:cycle:ppc-pthread|details]]
~~CL~~