====== Single-core PowerPC405 simulator ======






===== Description =====

This //Single-core PowerPC405 simulator// simulator includes a PowerPC 405 32-bit RISC CPU with a scalar 5-stage pipeline, and 
separated instruction and data caches. Both caches are connected to a main dram memory through a system bus, as shown on the figure below.

{{ simulators:cycle:ppc-score.png }}

The instruction cache which does not appear on the figure is embbeded within the //PowerPC 405 CPU// module.


===== How to get the simulator =====

This simulator is available at [[https://unisim.org/svn/public/components/CycleLevel/simulators/ppc-score]].

To compile, it requires to download the whole public branch of the repository which contains all the components composing the simulator. More information can be found on the [[download:Public Branch]] page.





===== Compatible Benchmarks and Tests =====

  * [[tools:benchmarks:MiBench Results]]

===== Modules composing the simulator =====

The figure below ... FIXME

{{ simulators:cycle:ppc-score_ports.png }}

More details are available for each module composing the simulator:
  * [[modules:cycle:processors:powerpc405:|PowerPC 405]]: The CPU embedding the 5-stage pipeline, and an instruction cache.
  * [[modules:cycle:network:cachewb:|Write-back Cache]]: A Write back data cache.
  * [[modules:cycle:network:dram:|DRAM Memory]]: The main memory of the simulator.
  * [[modules:cycle:network:bus:|System BUS]]:  The system bus connecting the caches to the main memory.

===== Services used by the simulator =====

{{ simulators:cycle:ppc-score_services.png }}

  * elf32-loader
  * linuxos
  * gdb-server debugger
  * inline debugger