====== Multi-Independant Core PowerPC ======







===== Description =====

This //Single-core PowerPC405 simulator// simulator includes several PowerPC 405 32-bit RISC CPUs with a scalar 5-stage pipeline, and separated instruction and data caches. Each processor is connected to its own instruction memory.

{{ ppc-mcore.png }}

The instruction cache which does not appear on the figure is embbeded within the //PowerPC 405 CPU// module.

A program should be loaded in each instruction memory connected to each processor. The whole global memory is fully shared, and cache coherency can be activated by allowing bus snooping.

===== How to get the simulator =====

This simulator is available at [[https://unisim.org/svn/public/components/CycleLevel/simulators/ppc-mcore]].

To compile, it requires to download the whole public branch of the repository which contains all the components composing the simulator. More information can be found on the [[download:Public Branch]] page.


===== Modules compopsing the simulator =====

  * [[modules:cycle:processors:powerpc405:|PowerPC 405]]
  * [[modules:cycle:network:cachewb:|Write-back Cache]]
  * [[modules:cycle:network:dram:|DRAM Memory]]
  * [[modules:cycle:network:bus:|System BUS]]

===== Services used by the simulator =====

  * elf32-loader
  * linuxos
  * gdb-server debugger
  * inline debugger