====== Single-core Arm v5te simulator ======



===== Description =====

This //Single-core Arm v5te simulator// simulator includes an Arm v5te 32-bit RISC CPU with a scalar 5-stage pipeline, and 
separated instruction and data caches. Both caches are connected to a main dram memory through a system bus, as shown on the figure below.

{{ simulators:cycle:arm-score.png }}

The instruction cache which does not appear on the figure is embbeded within the //Arm v5te CPU// module.

===== How to get the simulator =====

This simulator is available at [[https://unisim.org/svn/public/components/CycleLevel/simulators/arm-score]].

To compile, it requires to download the whole public branch of the repository which contains all the components composing the simulator. More information can be found on the [[download:Public Branch]] page.


===== Modules compopsing the simulator =====

FIXME missing paragraph

{{ simulators:cycle:arm-score_ports.png }}

  * [[modules:cycle:processors:armv5te:|Atm v5te]]
  * [[modules:cycle:network:cachewb:|Write-back Cache]]
  * [[modules:cycle:network:dram:|DRAM Memory]]
  * [[modules:cycle:network:bus:|System BUS]]

===== Services used by the simulator =====

{{ simulators:cycle:arm-score_services.png }}

  * elf32-loader
  * linuxos
  * gdb-server debugger
  * inline debugger