====== PowerPC 405 processor module ======

===== Description =====

This module implements a 32-bit RISC PowerPC 405 processor. The PowerPC 405 in-order five stage single issue execution pipeline is embedded into the module. The module also embeds an internal L1 instruction cache, the data cache should be instantiated as an external module.

The PowerPC 405 module has two pair of input and output port to connect to the instruction memory and the data memory hierarchy as shown in figure below.

{{ modules:cycle:processors:powerpc405:module.png }}

The whole pipeline of the PowerPC 405 was embedded in a single pipelined module because this pipeline is a simple in-order 5-stage pipeline. For more complex pipeline (out-of-order, prediction intensive, ...) the module should be split into several modules, communicating together around the pipelinestage boundaries.


===== Module details =====

  * [[Parameters]] of the module: Details on the module template parameters.
  * [[Interface]] of the module: Defines the module communication ports.
  * [[Internals]] of the module: Some details about the main internal data structures and algorithms.
  * [[Statistics]] of the module: List of the statistics gathered by the module.




===== Links =====

  * Source file in the repository:  [[https://unisim.org/svn/public/components/CycleLevel/packages/system/cpu/powerpc405/CpuPPC405.sim|CpuPPC405.sim]]
  * FIXME link  to the source documentation repository

===== Simulators using this module =====

  * [[simulators:cycle:ppc-score|Single-core PowerPC405 simulator]]
  * [[simulators:cycle:arm-score|Single-core Arm v5 te simulator]]
  * [[simulators:cycle:ppc-pth|PowerPC405 CMP]]