===== PowerPC 405 module interface =====

{{ modules:cycle:processors:powerpc405:module.png }}


==== Clocks ====

  * ''**inclock clock**'' \\ Input clock port to receive the cpu clock.


==== Module ports ====

  * ''**outport < memreq < Instruction, nIL1CachetoMemDataPathSize > > outIL1Data**'' \\ Output port used to send requests to the instruction memory hierarchy.
  * ''**inport < memreq < Instruction, nIL1MemtoCacheDataPathSize > > inIL1Data**'' \\ Input port receiving answers from the instruction memory hierarchy. Those answers correspond to previously sent requests.
  * ''**outport < memreq < Instruction, nDL1CPUtoCacheDataPathSize > > outDMEM**'' \\ Output port used to send requests to the data memory hierarchy.
  * ''**inport < memreq < Instruction, nDL1CachetoCPUDataPathSize > > inDMEM**'' \\ Input port receiving answers from the data memory hierarchy. Those answers correspond to previously sent requests.

==== Optional module ports ====

The CPU does not have any optional port.