====== MicroLib Cache Wrapper ======









===== Description =====

This module implements a wrapper to the cache modules defined in MicroLib. For more details of MicroLib caches, refer to the [[http://microlib.org|MicroLib]] website.

This wrapper module has two different sides. The side connected to the CPU (or to a lower level cache) and the side connected to the memory (or to a higher level cache). For the purpose of this documentation we’ll consider the port on the cpu side inCPU and outCPU as port connected to a cpu, and the port on the memory side inMEM and outMEM as memory ports as shown on the figure below.

{{ cache_wrapper.png }}

The wrapper module also includes some MicroLib ports (in green) to be connected to a MicroLib cache module.

The following MicroLib caches have currently successfully being wrapped:
  * Non-blocking cache (CacheWBNB)
  * Multi-port non-blocking cache with victim cache (CacheWBNBVCMultiPorted)
  * Multi-port non-blocking cache with timekeeping victim cache (CacheWBNBTKVCMultiPorted)
  * Non-blocking cache with stride prefetcher (CacheWBNBSP)
  * Non-blocking cache with content directed prefetcher (CacheWBNBCDP)
  * Non-blocking cache with content directed prefetcher and stride prefetcher (CacheWBNBCDPSP)
  * Non-blocking cache with tag prefetcher (CacheWBNBTP)

The following caches were not wrapped yet because they use a different interface:
  * Multi-port non-blocking cache with timekeeping (CacheWBNBTKMultiported)
  * Multi-port non-blocking cache with tag correlating prefetcher (CacheWBNBTCPMultiported)
  * Multi-port non-blocking cache with dead-block correlating prefetcher (CacheWBNBDBCPMultiported)


===== Module details =====

  * [[parameters]]
  * [[interface]]
  * [[internals]]

----

===== Links =====

  * Source file in the repository:  [[https://unisim.org/svn/public/components/CycleLevel/packages/system/memory/cache/MicrolibCacheWrapper.sim|MicrolibCacheWrapper.sim]]
  * FIXME link  to the source documentation repository


===== Simulators using this module =====

none yet.